wyvernSemi/pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

语言：C · GitHub 星标：155 · Fork：35

话题：bfm · c · cosim · ghdl · icarus-verilog · modelling · nvc · pcie

在 GitHub 上查看原仓库