sifive/RiscvSpecFormal

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

语言：Haskell · GitHub 星标：79 · Fork：6

话题：coq · formal-verification · hardware · hardware-designs · riscv · riscv-simulator

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