oscc-ip/sdram

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

语言：Scala · GitHub 星标：22 · Fork：3

话题：axi4 · fpga · sdram · tapeout · verilog

在 GitHub 上查看原仓库