muhammadaldacher/Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC

This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

语言：MATLAB · GitHub 星标：42 · Fork：13

话题：adc · cadence-virtuoso · dac · matlab · veriloga

在 GitHub 上查看原仓库