muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

语言：MATLAB · GitHub 星标：99 · Fork：15

话题：analog-design · cadence-virtuoso · matlab · pll · veriloga

在 GitHub 上查看原仓库