merledu/buraq_mini

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

语言：Scala · GitHub 星标：11 · Fork：6

话题：buraq-mini · chisel3 · open-mpw · risc-v · riscv32im

在 GitHub 上查看原仓库