killerglider/rv32ic-processor

Two-stage pipelined RV32I/C RISC-V processor in Chisel 6. Machine-mode privilege, CSRs, trap handling, memory-mapped UART/GPIO/timer. Verified with chiseltest + Verilator, synthesized for iCE40HX8K FPGA.

语言：Scala · GitHub 星标：3 · Fork：1

话题：chisel · fpga · hardware · ice40 · processor · risc-v · verilator · verilog

在 GitHub 上查看原仓库