dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

语言：SystemVerilog · GitHub 星标：497 · Fork：102

话题：asic · asic-design · async · cdc · cross-clock-domain · fifo · fifo-cache · fifo-queue

在 GitHub 上查看原仓库