chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

语言：C++ · GitHub 星标：476 · Fork：91

话题：antlr · antlr4-grammar · elaboration · linter · parser · parser-ast · preprocessor · python-api

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