ThalesGroup/risc-v-chisel-project

This is a starter template for your custom RISC-V project. It will allow you to leverage the Chisel HDL and RocketChip SoC generator to produce a RISC-V SoC with MMIO-mapped peripherals, DMA, and custom accelerators.

语言：Scala · GitHub 星标：3 · Fork：3

在 GitHub 上查看原仓库