JacobMcSeveney/ddr-resocket-multichannel-dma

Open-source multi-channel DDR DMA controller for FPGA: 4 write channels, 5 read channels, async FIFOs, address generation, and arbitration.

语言：HTML · GitHub 星标：84 · Fork：0

话题：adc · awg · axi4 · clc · cmp · ddr · dma · dspic

在 GitHub 上查看原仓库